Exploring the Philosophy of Technology and AI-Hardware Co-design
As a sci-fi lover and an active follower of new developments of technology, I am broadly interested in the Philosophy of Technology - how the advance of AI/ML will shape social conventions and create new paradigm. Specifically, with my research direction in computer architecture and systems, I am interested in advancing chip making process and architecture design which could play a significant role in such paradigm shift.
My first full-time job after undergraduate at NVIDIA as an ASIC power engineer exposed me to the entire process of chip making, including the architecture design, the synthesis and the physical design stage. As I found that my interests rooted deeply in computer architecture, I later moved to the company's architecture team, and eventually started pursuing my Ph.D. at Princeton.
What is the next big thing in computing and what can we architects do about it?
After exploring edge computing, value proximity and instruction/kernel scheduling, my current answer is "the advance of AI algorithms and the hardware development lagging behind it, both for acceleration and for safety precaution".
The scalability of AI models/agents are clearly bottlenecked by the current capabilities of hardware, but where is the upper limit of the hardware? What does a tailored AI-specific hardware look like? On the other hand, AI's interpretability is low - can we handle the potential threat of AI to the human society from the hardware side?
These are the questions that I am broadly interested in and that my current and future research tries to answer. Overall, I want to seek ways to design and build chips that do good to the human kind: aiding useful AI agents and preventing potential threats.
How will AI shape hardware-software co-design?
The rise of AI agent introduces a new pattern of hardware computing and memory access which is so important that everything should be optimized for it. My recent papers explore new AI application's implication on hardware, and propose analytical models to find best application performance under different hardware configurations.
How will the momentous rise of AI shape the semiconductor market and the chip making process?
New challenges are introduced by AI such as safety risks, export control requirements, and hardware market contention. These scenarios call for a need to explicitly differentiate chips that target AI application's performance from other applications by tuning the hardware resources available.
How can we stop AI threat on the hardware level?
Because AI models are hard to interpret, in the near future we might start to worry about AI agents that are smarter than us posing threats to the human world. AI alignment is yet an active research field in AI safety, but most solutions are within the software regime, which the AI can easily break.
My ongoing research studies:
In the future, I will continue my research at the intersection of AI + hardware architecture, specifically on understanding AI application's "footprint" (behaviors or patterns) on hardware, and exploiting it to either accelerate or throttle the performance of the application depending on the need.
I will continue to do meaningful research in the AI + hardware field that explores new solutions for the rest of my Ph.D. and afterwards. I want to build new hardware/software solutions that respond quickly to the new waves of technology.